上节回顾FSM分类34ARCHITECTUREbehavOFADCINTISTYPEstatesIS(st0,st1,st2,st3,st4);--定义各状态子类型SIGNALcurrent_state,next_state:states;SIGNALREGL:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALLOCK:STD_LOGIC;--转换后数据输出锁存时钟信号BEGINADDA<=‘0’;--当ADDA<=‘0’，模拟信号进入通道IN0；Q<=REGL;LOCK0<=LOCK;COM:PROCESS(current_state,EOC)--主控组合进程描述BEGIN--规定各状态转换方式CASEcurrent_stateISWHENst0=>ALE<='0';START<='0';LOCK<='0';OE<='0';next_state<=st1;--0809初始化WHENst1=>ALE<='1';START<='1';LOCK<='0';OE<='0';next_state<=st2;--启动采样WHENst2=>ALE<='0';START<='0';LOCK<='0';OE<='0';IF(EOC='1')THENnext_state<=st3;--EOC=1表明转换结束ELSEnext_state<=st2;ENDIF;--转换未结束，继续等待WHENst3=>ALE<='0';START<='0';LOCK<='0';OE<='1';next_state<=st4;--开启OE,输出转换好的数据WHENst4=>ALE<=‘0’;START<=‘0’;LOCK<=‘1’;OE<=‘1’;next_state<=st0;--锁存数据WHENOTHERS=>next_state<=st0;ENDCASE;ENDPROCESSCOM;7891011121314常用vhdl语言描述FSM的建立过程1617WHENst4=>IFDATAIN='1'THENQ<="11101";ELSEQ<="01101";ENDIF;WHENOTHERS=>Q<="00000";ENDCASE;ENDPROCESSCOM1;ENDbehav;192021也可以这样写还可以这样写，组合进程+辅助进程Moore/Mealy区别LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYS_MACHINEISPORT(CLK,RESET，STATE_INPUT:INSTD_LOGIC;COMB_OUTPUT:OUTSTD_LOGIC);ENDS_MACHINE;ARCHITECTUREBEHVOFS_MACHINEISTYPEFSM_STIS(idle,first_one,second_1,third_one);SIGNALCURRENT_STATE,NEXT_STATE:FSM_ST;BEGINREG:PROCESS(RESET,CLK)BEGINIFRESET='1'THENCURRENT_STATE<=idle;ELSIFCLK='1'ANDCLK'EVENTTHENCURRENT_STATE<=NEXT_STATE;ENDIF;ENDPROCESS;COM:PROCESS(CURRENT_STATE,STATE_INPUT)BEGINCASECURRENT_STATEISWHENidle=>IFSTATE_INPUT='0'THENNEXT_STATE<=idle;COMB_OUTPUT<=‘0';ELSENEXT_STATE<=first_one;COMB_OUTPUT<=‘0';ENDIF;WHENfirst_one=>IFSTATE_INPUT='0'THENNEXT_STATE<=idle;COMB_OUTPUT<=‘0';ELSENEXT_STATE<=second_one;COMB_OUTPUT<=‘0';ENDIF;WHENsecond_one=>IFSTATE_INPUT='0'THENNEXT_STATE<=idle;COMB_OUTPUT<=‘0';ELSENEXT_STATE<=third_one;COMB_OUTPUT<=‘1';ENDIF;WHENthird_one=>IFSTATE_INPUT='0'THENNEXT_STATE<=idle;COMB_OUTPUT<=‘0';ELSENEXT_