上节回顾3.3使用VHDL语言描述基本逻辑电路3.3.1RTL电路模型一点建议组合逻辑电路组合逻辑-多选电路带有优先级的多选电路LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYpri_muxISPORT(input_a：INstd_logic；input_b：INstd_logic；input_c：INstd_logic；input_d：INstd_logic；select_a：INstd_logic；select_b：INstd_logic；select_c：INstd_logic；pout：OUTstd_logic)；ENDpri_mux；ARCHITECTUREpri_muxOFpri_muxISBEGINPROCESS（input_a，input_b，input_c，input_d，select_a，select_b，select_c）BEGINIFselect_a=‘1’THENpout<=input_a；ELSIFselect_b=‘1’THENpout<=input_b；ELSIFselect_c=‘1’THENpout<=input_c；ELSEpout<=input_d；ENDIF；ENDPROCESS；ENDpri_mux；电子与通信工程系无优先级的多选电路LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYmuxISPORT(input_a：INstd_logic；input_b：INstd_logic；input_c：INstd_logic；input_d：INstd_logic；sel：INstd_logic_vector（1downto0）；pout：OUTstd_logic)；ENDmux；ARCHITECTUREmuxOFmuxISBEGINPROCESS（input_a，input_b，input_c，input_d，sel）BEGINCASEselISWHEN“00”=>pout<=input_a；WHEN“01”=>pout<=input_b；WHEN“10”=>pout<=input_c；WHENothers=>pout<=input_d；ENDCASE；ENDPROCESS；ENDmux；电子与通信工程系组合逻辑-译码器LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYdecoderISPORT(Ain：INstd_logic_vector（2downto0）；en：INstd_logic；Yout：OUTstd_logic_vector（7downto0））；ENDdecoder；ARCHITECTUREdecoderOFdecoderISBEGINPROCESS（Ain，en）BEGINIFen=‘0’THENYout<=（others=>‘0’）；ELSECASEAinISWHEN“000”=>Yout<=“00000001”；WHEN“001”=>Yout<=“00000010”；WHEN“010”=>Yout<=“00000100”；WHEN“011”=>Yout<=“00001000”；WHEN“100”=>Yout<=“00010000”；WHEN“101”=>Yout<=“00100000”；WHEN“110”=>Yout<=“01000000”；WHEN“111”=>Yout<=“10000000”；WHENothers=>Yout<=（others=>‘0’）；ENDCASE；ENDIF；ENDPROCESS；ENDdecoder；电子与通信工程系算术运算电路Info:Longesttpdfromsourcepin"operand_b[2]"todestinationpin"result[4]"is12.706ns四位乘法器Info:Longesttpdfromsourcepin"operand_a[3]"todestinationpin"result[5]"is17.488ns关系运算电路LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcomparerISPORT(a:INstd_logic;b:INstd_logic;equal:OUTstd_logic;greatthan:OUTstd_logic;lessthan:OUTstd_logic);ENDcomparer;