第4章电子系统设计实践（一）<EDA技术与应用>课程讲义本章内容4位加法计数器设计（一）4位加法计数器设计（一）:图4位加法计数器设计（二）4位加法计数器设计（二）:图4位加法计数器设计（三）4位加法计数器设计（三）:图8位数码管显示扫描电路设计K1…K8为数码管的位控信号，对应FPGA的PIO41、40、39、38、37、36、35、34LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYSCAN_LEDISPORT(CLK:INSTD_LOGIC;SG:OUTSTD_LOGIC_VECTOR(6DOWNTO0);--段控制信号输出BT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));--位控制信号输出END;ARCHITECTUREoneOFSCAN_LEDISSIGNALCNT8:STD_LOGIC_VECTOR(2DOWNTO0);SIGNALA:INTEGERRANGE0TO15;BEGINP1:PROCESS(CNT8)BEGINCASECNT8ISWHEN"000"=>BT<="00000001";A<=1;WHEN"001"=>BT<="00000010";A<=3;WHEN"010"=>BT<="00000100";A<=5;WHEN"011"=>BT<="00001000";A<=7;WHEN"100"=>BT<="00010000";A<=9;WHEN"101"=>BT<="00100000";A<=11;WHEN"110"=>BT<="01000000";A<=13;WHEN"111"=>BT<="10000000";A<=15;WHENOTHERS=>NULL;ENDCASE;ENDPROCESSP1;P2:PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENCNT8<=CNT8+1;ENDIF;ENDPROCESSP2;P3:PROCESS(A)--译码电路BEGINCASEAISWHEN0=>SG<="0111111";WHEN1=>SG<="0000110";WHEN2=>SG<="1011011";WHEN3=>SG<="1001111";WHEN4=>SG<="1100110";WHEN5=>SG<="1101101";WHEN6=>SG<="1111101";WHEN7=>SG<="0000111";WHEN8=>SG<="1111111";WHEN9=>SG<="1101111";WHEN10=>SG<="1110111";WHEN11=>SG<="1111100";WHEN12=>SG<="0111001";WHEN13=>SG<="1011110";WHEN14=>SG<="1111001";WHEN15=>SG<="1110001";WHENOTHERS=>NULL;ENDCASE;ENDPROCESSP3;END;端口定义位选进程计数进程译码进程本试验思考13分频器电路设计以下内容为正文的引用，可不阅读。返回STD_LOGIC的取值